1. Field of the Invention
The present invention generally relates to semiconductor devices, and more particularly, the present invention relates to a data line layout for signal transmission in a semiconductor memory device and to a method of forming the same.
2. Description of the Related Art
A semiconductor memory device generally includes a memory cell array region for storing data and a peripheral circuit region for accessing that memory cells and conducting various process operations. The memory cell array region generally includes a plurality of data blocks having intersecting word lines and bit lines. A decoder region is operatively interposed between the memory cell array region and the peripheral circuit region to transmit address and data signals there between. The decoder region is generally divided into a row decoder region for interfacing the word lines of the memory cell array region with the peripheral circuit region, and a column decoder region for interfacing the bit lines of the memory cell array region with the peripheral circuit region.
FIG. 1 is a plan view illustrating the layout of a conventional semiconductor memory device.
Referring to FIG. 1, the conventional semiconductor memory device of this example includes a data block DB located at intersections of a plurality of word lines WL<0:31> and a plurality of bit lines BL<0:n>. Also according to this example, the even numbered word lines WL extent to a first row decoder Row DEC1, and the odd numbered word lines WL extend to a second row decoder Row DEC2, where the first and second row decoders Row DEC1 and Row DEC2 are located on opposite sides of the data block DB. Likewise, the even numbered bit lines BL extent to a first column decoder Column DEC1, and the odd numbered bit lines BL extend to a second column decoder Column DEC2, where the first and second column decoders Column DEC1 and Column DEC2 are located on opposite sides of the data block DB.
In an alternative layout (not shown), a single row decoder is provided on one side of the data block DB and coupled to all the word lines WL, and a single column decoder is provided on one side of the data block DB and couple to all the bit lines. However, by providing two row decoders and two column decoders on opposite sides of the data block DB as in FIG. 1, the pitch between the bit lines and the pitch between the word lines can be more easily narrowed.
FIG. 2 is a plan view illustrating the word line layout of a data block of a conventional semiconductor memory device. In this example, each data block of the memory device includes thirty-two word lines WL<0:31>.
As illustrated in FIG. 2, odd-number word lines among word lines WL00-WL31 extend to a right decoder region, and even-number word lines among word lines WL00-31 extend to a left decoder region. Each word line includes a pad extension portion 12 which extend in a given direction for connecting to a peripheral device through wiring. Since the even-number word lines and the odd-number word lines are alternately connected to the left side decoder region and the right side decoder region, a relatively large interval between the pad extension portions 12 can be obtained. However, when a line width of the word line is reduced to less than the limitation value that is defined through the photo-etching process, the interval 10 between the adjacent pad extension portions 12 is reduced, which can make it difficult maintain sufficient spacing to allow for formation of contact patterns on the pad extension portions 12.